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PE4272
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4272 SPDT switch. The RF common port is
connected through a 75 ? transmission line to the
bottom F connector, J2. Port 1 and Port 2 are
connected through 75 ? transmission lines to two F
connectors on either side of the board, J1 and J3. A
through transmission line connects F connectors J4
and J5. This transmission line can be used to
estimate the loss of the PCB over the environmental
conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide with ground plane model using
a trace width of 0.021”, trace gaps of 0.030”,
dielectric thickness of 0.028”, copper thickness of
0.0021” and ε r of 4.3.
J6 provides a means for controlling the DC inputs to
the device. The lower right pin (J6-2) is connected
to the device CTRL input. The upper right pin (J6-1)
is connected to the device V DD input. Footprints for
decoupling capacitors are provided on both CTRL
and V DD traces. It is the responsibility of the
customer to determine proper supply decoupling for
their design application. Removing these
components from the evaluation board has not been
shown to degrade RF performance.
?2005 Peregrine Semiconductor Corp. All rights reserved.
Figure 4. Evaluation Board Layouts
Peregrine specification 101/0243
Figure 5. Evaluation Board Schematic
Peregrine specification 102/0309
Document No. 70-0173-03 │ UltraCMOS? RFIC Solutions
Page 4 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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